menuconfig MTD_SPI_NOR
	tristate "SPI-NOR device support"
	depends on MTD
	help
	  This is the framework for the SPI NOR which can be used by the SPI
	  device drivers and the SPI-NOR device driver.

if MTD_SPI_NOR

config MTD_MT81xx_NOR
	tristate "Mediatek MT81xx SPI NOR flash controller"
	depends on HAS_IOMEM
	help
	  This enables access to SPI NOR flash, using MT81xx SPI NOR flash
	  controller. This controller does not support generic SPI BUS, it only
	  supports SPI NOR Flash.

config MTD_SPI_NOR_USE_4K_SECTORS
	bool "Use small 4096 B erase sectors"
	default y
	help
	  Many flash memories support erasing small (4096 B) sectors. Depending
	  on the usage this feature may provide performance gain in comparison
	  to erasing whole blocks (32/64 KiB).
	  Changing a small part of the flash's contents is usually faster with
	  small sectors. On the other hand erasing should be faster when using
	  64 KiB block instead of 16 × 4 KiB sectors.

	  Please note that some tools/drivers/filesystems may not work with
	  4096 B erase size (e.g. UBIFS requires 15 KiB as a minimum).

config SPI_ATMEL_QUADSPI
	tristate "Atmel Quad SPI Controller"
	depends on ARCH_AT91 || (ARM && COMPILE_TEST)
	depends on OF && HAS_IOMEM
	help
	  This enables support for the Quad SPI controller in master mode.
	  This driver does not support generic SPI. The implementation only
	  supports SPI NOR.

config SPI_CADENCE_QUADSPI
	tristate "Cadence Quad SPI controller"
	depends on OF && ARM
	help
	  Enable support for the Cadence Quad SPI Flash controller.

	  Cadence QSPI is a specialized controller for connecting an SPI
	  Flash over 1/2/4-bit wide bus. Enable this option if you have a
	  device with a Cadence QSPI controller and want to access the
	  Flash as an MTD device.

config SPI_FSL_QUADSPI
	tristate "Freescale Quad SPI controller"
	depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE || COMPILE_TEST
	depends on HAS_IOMEM
	help
	  This enables support for the Quad SPI controller in master mode.
	  This controller does not support generic SPI. It only supports
	  SPI NOR.

config SPI_HISI_SFC
	tristate "Hisilicon FMCV100 SPI-NOR Flash Controller(SFC)"
	depends on ARCH_HISI || ARCH_HISI_BVT || COMPILE_TEST
	depends on HAS_IOMEM && HAS_DMA
	help
	  This enables support for hisilicon flash memory contrller ver100
	  (FMCV100)- SPI-NOR flash controller.

config SPI_NXP_SPIFI
	tristate "NXP SPI Flash Interface (SPIFI)"
	depends on OF && (ARCH_LPC18XX || COMPILE_TEST)
	depends on HAS_IOMEM
	help
	  Enable support for the NXP LPC SPI Flash Interface controller.

	  SPIFI is a specialized controller for connecting serial SPI
	  Flash. Enable this option if you have a device with a SPIFI
	  controller and want to access the Flash as a mtd device.

config MTD_SPI_IDS
    bool "SPI Flash Timing Cycles Probe Function"
    default n
    help
      This option enables hisfc300/hisfc350 used spi flash timing cylces
      probe function.
      If your use hisfc300 and hisfc350, this function should be select.

config CLOSE_SPI_8PIN_4IO
	bool "Close SPI device Quad SPI mode for some 8PIN chip"
	default y if ARCH_HISI_BVT
	help
	Hifmcv100 and Hisfcv350 support Quad SPI mode and Quad&addr SPI mode.
	But some 8PIN chip does not support this mode when HOLD/IO3 PIN
	was used by reset operation.
	Usually, your should not config this option.

config HISI_SPI_BLOCK_PROTECT
	bool "Hisilicon Spi Nor Device BP(Block Protect) Support"
	depends on SPI_HISI_SFC
	default y if SPI_HISI_SFC
	help
	  HISI SFC supports BP(Block Protect) feature to preestablish a series
	  area to avoid writing and erasing, except to reading. With this macro
	  definition we can get the BP info which was setted before. The
	  BOTTOM/TOP bit is setted to BOTTOM, it means the lock area starts
	  from 0 address.

source "drivers/mtd/spi-nor/hisfc350/Kconfig"

endif # MTD_SPI_NOR
